Meta
ASIC Engineer, Design Verification
$146K–$209K
Sunnyvale, CA +1 · Full-time · Posted Jul 2, 2026
- Location
- Sunnyvale, CA
Austin, TX - Experience
- 6+ years in each of the two verification areas stated in the qualifications.
- Education
- Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience.
About the job
Verifies ASIC IP and SoC designs for Meta data center applications, from planning and testbench development through debugging and verification closure.
What you'll do
- Define verification plans, develop testbenches and functional tests, and drive verification to closure against coverage metrics.
- Debug and resolve design failures with Design teams and collaborate with Model, Emulation, and Silicon validation teams.
- Improve verification methods, tools, and flows; use simulation, Formal, and Emulation approaches.
What they ask for
- Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience.
- 6+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification.
- 6+ years of IP/sub-system and/or SoC-level verification using SystemVerilog UVM/OVM-based methodologies.
- Experience with EDA tools and scripting, revision control systems, verification infrastructure, and the full verification cycle.
Nice to have
- Experience with data-center designs, first-pass ASIC success, micro-architectural performance verification, or GPU/CPU verification.
- Experience with ARM/RISC-V, high-speed interfaces, UVM environments from scratch, SV Assertions, Formal, or Emulation.
Pay
$146,000/year to $209,000/year (base salary)
Tools
SystemVerilog, UVM, C/C++, Python, TCL, Perl, Shell, Mercurial(Hg), Git or SVN
AI focus
The role verifies data-center designs that may include AI/ML applications; AI/ML-specific work is not otherwise described.
Model-written summary · the original posting is authoritative