Meta
ASIC Engineer, Formal Verification
$178K–$250K
Sunnyvale, CA +1 · Full-time · Posted Oct 20, 2026
- Location
- Sunnyvale, CA
Austin, TX - Experience
- 8+ years in Design Verification; 5+ years in Formal Verification.
- Education
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
About the job
Leads formal verification for complex ASIC IP and SoCs used in Meta data center applications, from methodology and test planning through verification sign-off.
What you'll do
- Provide technical leadership and establish formal verification methodology across block and top levels.
- Define verification scope, build reusable environments, and close coverage at IP, subsystem, and SoC levels.
- Partner with architecture and design teams on specifications and implementation, and evaluate EDA solutions.
What they ask for
- Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience.
- 8+ years of experience in Design Verification and 5+ years of experience in Formal Verification.
- Experience with formal verification applications, complex SoCs, and verification methodologies; fluency in SystemVerilog and SVA.
- Proficiency in Python, Perl, or Tcl; experience with JasperGold or VC-Formal.
Pay
$178,000/year to $250,000/year USD base salary
Tools
SystemVerilog, SVA, Python, Perl, Tcl, JasperGold, VC-Formal
Model-written summary · the original posting is authoritative