ASIC Engineer, Implementation

What you'll do

• Own ASIC implementation flows, including synthesis, timing analysis, verification, design-for-test, and tape-out sign-off.
• Develop reusable implementation methodologies, constraints, scripts, and automation; drive timing closure and generate SoC floorplans.
• Partner with architecture, RTL, physical design, and other teams to resolve implementation risks and guide design trade-offs.

What they ask for

• Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience.
• 8+ years of ASIC implementation experience, including logic synthesis, static timing analysis, and timing closure for complex SoC or custom ASIC designs.
• Experience with synthesis and implementation EDA tools; synthesis constraints including SDC and UPF; and timing closure across multi-million-gate designs with multiple clock domains.
• Experience developing implementation automation using Tcl or Python, and defining sign-off criteria and leading tape-out execution.

Nice to have

• Familiarity with physical-aware synthesis and early floorplan co-design.
• Experience with custom ASIC implementation for data center, AI accelerator, or high-performance computing applications.

Pay

$178,000/year to $250,000/year + bonus + equity

Tools

Synopsys Design Compiler, Fusion Compiler, Cadence Genus, SDC, UPF, Tcl, Python

AI focus

Implements custom ASICs for infrastructure that powers AI platforms; relevant experience includes ASICs for AI accelerators.