Meta
ASIC Engineer, Performance Architecture and Modeling
$114K–$172K
Sunnyvale, CA +1 · Full-time · Posted Jul 24, 2026
- Location
- Sunnyvale, CA
Austin, TX - Experience
- 2+ years in ASIC design, silicon engineering, or a related technical field.
- Education
- Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta.
About the job
Defines architecture and performance strategy for custom infrastructure ASICs, developing models and workloads to guide design decisions and meet throughput, latency, and efficiency targets.
What you'll do
- Explore microarchitectural trade-offs and develop cycle-accurate or transaction-level performance models.
- Build C++ models, workloads, kernels, and benchmarking methods for performance analysis.
- Collaborate across architecture, design, software, and systems teams to guide specifications and resolve performance gaps.
What they ask for
- Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience; degree must be completed before joining.
- 2+ years of experience in ASIC design, silicon engineering, or a related technical field.
- Proficiency in C++ and Python.
- Experience in ASIC performance modeling, microarchitectural analysis, or pre-silicon simulation for custom silicon or SoC designs.
Nice to have
- Experience analyzing data center, AI accelerator, or high-performance computing workloads on custom silicon.
- Experience with SystemC, CUDA or equivalent GPU programming frameworks, post-silicon validation, or PPA-driven optimization.
Pay
$114,000/year to $172,000/year USD (base salary)
Tools
C++, Python, SystemC, CUDA, SystemVerilog, VHDL
AI focus
Develops and analyzes AI-chip models and machine-learning training and inference workloads, including kernels and performance analysis.
Model-written summary · the original posting is authoritative