Meta
ASIC Engineer, Power
$146K–$209K
Sunnyvale, CA +1 · Full-time · Posted Jul 27, 2026
- Location
- Sunnyvale, CA
Austin, TX - Experience
- 6+ years of experience in ASIC design or physical design focused on power analysis, power optimization, or power signoff.
- Education
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
About the job
Develops and maintains EDA power-analysis and optimization infrastructure for Meta’s custom ASIC designs, supporting power estimation, signoff, and closure.
What you'll do
- Develop power analysis flows, methodology, and automation for ASIC design stages.
- Collaborate with design and verification teams to identify power inefficiencies and drive power closure.
- Evaluate EDA tools, define power budgets, and communicate power metrics and risks.
What they ask for
- Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience.
- Experience developing or maintaining EDA power-analysis flows and using power intent languages such as UPF or CPF.
- Experience scripting in Python, Tcl, or shell to automate EDA workflows.
- Experience collaborating across RTL design, physical design, and verification to drive power closure.
Nice to have
- Familiarity with custom or semi-custom flows for high-performance computing or data center silicon.
- Experience with low-power design techniques or large-scale internal EDA infrastructure tooling.
Pay
$146,000/year to $209,000/year (base salary)
Tools
Synopsys PrimePower, Cadence Voltus, UPF, CPF, Python, Tcl
Model-written summary · the original posting is authoritative