Meta
ASIC Engineer, Power
$114K–$172K
Sunnyvale, CA +1 · Full-time · Posted Sep 24, 2026
- Location
- Sunnyvale, CA
Austin, TX - Experience
- 6+ years; no stated alternative.
- Education
- Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience; degree must be completed prior to joining Meta.
About the job
Develops and maintains EDA power-analysis and optimization flows and methodologies for Meta’s custom ASIC designs, supporting power estimation, signoff, and closure.
What you'll do
- Build and improve power-analysis flows, EDA automation, and power-intent verification.
- Define power methodologies and budgets; collaborate with design teams to identify and resolve power issues.
- Evaluate EDA tools and guide engineers and stakeholders on power analysis results and practices.
What they ask for
- Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience; degree must be completed before joining.
- 6+ years of ASIC design or physical design experience focused on power analysis, optimization, or signoff.
- Experience developing or maintaining power-analysis EDA flows and applying UPF or CPF across RTL-to-GDSII flows.
- Experience scripting in Python, Tcl, or shell and collaborating across RTL design, physical design, and verification.
Nice to have
- Experience qualifying EDA tools or methodologies in production silicon; familiarity with custom or semi-custom HPC or data-center silicon flows.
- Experience with low-power techniques or large-scale internal EDA infrastructure automation.
Pay
$114,000/year to $172,000/year (base salary); bonus and equity amounts not stated.
Tools
Synopsys PrimePower, Cadence Voltus, UPF, CPF, Python, Tcl, shell, RTL-to-GDSII
Model-written summary · the original posting is authoritative