ASIC Engineering Intern, Design Verification (Silicon Engineering)

What you'll do

• Write SystemVerilog test benches and tests, and build or extend UVM verification components.
• Help plan verification, run simulations, debug failures, and track functional and code coverage.
• Write Python scripts to automate regressions and collaborate with design and methodology engineers.

What they ask for

• Currently has or is pursuing a Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.
• Coursework or project experience in digital logic design and experience with Verilog or SystemVerilog.
• Object-oriented programming experience and Python scripting experience.
• Must obtain and maintain work authorization in the country of employment and intend to return to a full-time degree program after the internship.

Nice to have

• Exposure to UVM or another class-based verification methodology; familiarity with constrained-random stimulus, functional coverage, assertions, and scoreboarding.
• Experience with RTL simulators and waveform debugging, or projects in image processing, computer vision, signal processing, AI/ML hardware acceleration, or digital design and verification.

Pay

$6,660/month to $12,014/month (compensation type not stated)

Tools

SystemVerilog, UVM, Python, C++, Java, VCS, Xcelium, Questa

AI focus

The role may involve verification of AI/ML hardware acceleration as part of vision and image-processing IP.