Meta
ASIC Implementation Engineer, Static Verification
$146K–$209K
Sunnyvale, CA · Full-time · Posted Sep 25, 2026
- Experience
- 6+ years of experience in static verification tools.
- Education
- Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience.
About the job
Implements and verifies ASIC front-end designs from RTL to optimized gate-level netlists for data center SoCs and IP.
What you'll do
- Run RTL lint, clock and reset domain crossing checks, and DFT analysis; collaborate with designers on findings and signoff.
- Run logic and physical synthesis, optimizing netlists for timing, area, and power.
- Develop automation scripts and methodologies, and support design handoffs with engineering teams.
What they ask for
- 6+ years of experience in static verification tools.
- Experience with lint, clock and reset domain crossing, and SoC CDC signoff.
- Experience with RTL design using SystemVerilog or another HDL, and front-end ASIC flows.
- Scripting and programming experience using Perl/Python, TCL, and Make.
Nice to have
- Experience with Design Compiler, Spyglass, PrimeTime, Formality, or equivalent tools.
- Knowledge of timing/physical libraries and SRAM memories.
Pay
$146,000/year to $209,000/year USD base salary
Tools
SystemVerilog, Perl/Python, TCL, Make, Design Compiler, Spyglass, PrimeTime, Formality
Model-written summary · the original posting is authoritative