Design Verification Engineer, Silicon

What you'll do

• Develop verification plans, UVM testbenches, and coverage models for RTL blocks, subsystems, and SoCs.
• Maintain simulation, regression, and automated test infrastructure; debug failures and perform formal verification.
• Coordinate verification and pre-silicon test content with design, architecture, software, firmware, and post-silicon teams.

What they ask for

• Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience.
• 6+ years of digital design verification experience, including UVM-based constrained-random testbenches.
• 6+ years of experience with hardware description and verification languages, including SystemVerilog and/or VHDL.
• Experience with functional and code coverage, RTL simulation debugging, scripting for test automation, HW/SW interoperability verification, and firmware validation.

Nice to have

• Experience with post-silicon validation, hardware bring-up, or consumer/mobile/wearable SoC verification, including low-power techniques.
• Familiarity with formal verification and agentic AI flows; experience with CPUs, AI accelerators, security, interconnects, memory controllers, or full-SoC verification.

Pay

$146,000/year to $209,000/year USD base salary; bonus and equity also stated, with no amounts specified.

Tools

UVM, SystemVerilog, VHDL, Python, Perl

AI focus

Verifies custom AI silicon, including AI accelerators; familiarity with agentic AI flows is noted.