Meta
Design Verification Engineer, Silicon
$146K–$209K
Sunnyvale, CA +3 · Full-time · Posted Sep 2, 2026
- Location
- Sunnyvale, CA
Redmond, WA
Austin, TX
San Diego, CA - Experience
- 6+ years in digital design verification and 6+ years with hardware description and verification languages.
- Education
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
About the job
Develops and executes verification strategies for custom AR/VR silicon, validating digital logic blocks and subsystems from specification through tape-out.
What you'll do
- Develop UVM testbenches, verification plans, coverage models, and automated regression infrastructure for RTL designs.
- Perform formal verification and debug simulations; collaborate with design, firmware, and post-silicon teams.
- Track verification progress and improve reusable verification methods and infrastructure.
What they ask for
- Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience.
- 6+ years of digital design verification experience, including UVM-based constrained-random testbenches for complex RTL blocks or subsystems.
- 6+ years of experience with SystemVerilog and/or VHDL.
- Experience defining and closing coverage metrics, debugging RTL simulations, and using Python or Perl for automation.
Nice to have
- Experience with post-silicon validation or hardware bring-up; silicon verification for mobile, wearable, or consumer electronics SoCs and low-power techniques.
- Knowledge of AR/VR-relevant subsystems or familiarity with formal verification tools and methodologies.
Pay
$146,000/year to $209,000/year USD base salary
Tools
UVM, RTL, SystemVerilog, VHDL, Python, Perl
Model-written summary · the original posting is authoritative