Meta
Digital Design Engineer, Interconnect
$178K–$250K
Sunnyvale, CA +2 · Full-time · Posted Oct 6, 2026
- Location
- Sunnyvale, CA
Redmond, WA
Austin, TX - Experience
- 8+ years as a Hardware Design Engineer for production silicon shipped in volume.
- Education
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
About the job
Designs and delivers ASIC interconnect and fabric IP, from architecture and microarchitecture through RTL, while collaborating to meet power, performance, and implementation targets.
What you'll do
- Develop ASIC digital microarchitecture, RTL, and design verification for complex IP and subsystems.
- Analyze power and performance, and work with architecture, verification, physical design, and design-for-test teams to meet targets.
- Define and implement interconnect architecture, including topology, protocols, buffering, arbitration, and performance budgets.
What they ask for
- Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience.
- 8+ years of experience as a Hardware Design Engineer for production silicon shipped in volume.
- Experience in digital design microarchitecture and RTL coding, including developing interconnect/NoC/fabric IP from architecture specification through RTL delivery.
- Experience with interconnect implementation, configurator and generation flows, and cross-functional technical leadership or mentoring.
Pay
$178,000/year to $250,000/year USD base salary; bonus and equity amounts not stated
Tools
ASIC, RTL, interconnect/NoC/fabric IP, industry-standard interconnect and bus protocols
AI focus
Use AI tools to optimize or redesign workflows and produce measurable impact; follow responsible, ethical AI practices; continue developing AI skills, including prompt/context engineering and agent orchestration.
Model-written summary · the original posting is authoritative