Meta
Digital Design Engineer, SoC Chassis
$146K–$209K
Sunnyvale, CA +2 · Full-time · Posted Oct 6, 2026
- Location
- Sunnyvale, CA
Redmond, WA
Austin, TX - Experience
- 6+ years as a hardware design engineer for production silicon shipped in volume.
- Education
- Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience.
About the job
Designs and integrates digital ASIC/SoC infrastructure IP and subsystems, developing microarchitecture and RTL while helping meet power and performance targets.
What you'll do
- Develop ASIC digital microarchitecture and RTL for complex IPs and subsystems.
- Analyze power and performance and help achieve design targets.
- Work with architecture, verification, physical design, and design-for-test teams on algorithm mapping, integration requirements, and design decisions.
What they ask for
- Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience.
- 6+ years of experience as a hardware design engineer for production silicon shipped in volume.
- Experience in digital design microarchitecture, RTL coding, and microarchitecture development.
- Experience communicating technical design decisions and trade-offs across teams.
Nice to have
- Experience with infrastructure IP, subsystem implementation or integration, or microcontroller clusters.
- Demonstrated ability to use AI tools to improve workflows, apply responsible AI practices, and continue developing AI skills.
Pay
$146,000/year to $209,000/year USD base salary; bonus and equity amounts not stated.
Tools
ASIC, RTL, AI tools
AI focus
Use AI tools to optimize or redesign workflows and produce measurable impact; follow responsible, ethical AI practices; and develop skills such as prompt/context engineering and agent orchestration.
Model-written summary · the original posting is authoritative