Meta
DPU IO Architect, Infrastructure Silicon
$178K–$250K
Sunnyvale, CA +1 · Full-time · Posted Oct 2, 2026
- Location
- Sunnyvale, CA
Austin, TX - Experience
- 8+ years required; posting also lists 15+ years in a separate qualification section.
- Education
- Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience; PhD listed in a separate qualification section.
About the job
Architect the DPU I/O subsystem and hardware/software interfaces, from early design through implementation and silicon bring-up.
What you'll do
- Own I/O architecture covering PCIe, DMA and offload engines, virtualization, confidential computing, and system management.
- Define hardware, firmware, and software responsibilities and the interfaces between them; collaborate with firmware, driver, RTL, design, DV, and PD teams.
- Evaluate performance, power, and area trade-offs, support integration, and help bring up the I/O subsystem in silicon.
What they ask for
- Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience.
- 8+ years of relevant industry experience architecting I/O and system subsystems and hardware/software interfaces for NIC/DPU or comparable ASICs.
- Experience with PCIe protocols and capabilities, I/O virtualization, scheduling and QoS, cryptography and inline encryption, x86 and/or ARM system architecture, and data center I/O workloads.
- Experience independently driving architectural decisions and influencing their direction through data.
Nice to have
- PhD in Computer Science, Computer Engineering or Electrical Engineering; 15+ years of relevant industry experience.
- Experience with PCIe endpoints and root complexes, HDL and simulation, Python automation, performance modeling, system management, DMA/offload accelerators, post-silicon validation, or Confidential Computing protocols.
Pay
$178,000/year to $250,000/year (base salary)
Tools
PCIe, SR-IOV, SIOV, AES-XTS, AES-GCM, SystemVerilog, VHDL, Python
Model-written summary · the original posting is authoritative