Meta
DPU Power Architect, Infrastructure Silicon
$178K–$250K
Sunnyvale, CA +1 · Full-time · Posted Oct 2, 2026
- Location
- Sunnyvale, CA
Austin, TX - Experience
- 15+ years of relevant industry experience in power architecture and power modeling for high-performance SoCs.
- Education
- Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience. The posting also lists a PhD in Computer Science, Computer Engineering, or Electrical Engineering.
About the job
Leads power modeling and architectural optimization for Meta DPU designs, from workload analysis and early estimates through RTL, gate-level analysis, and silicon correlation.
What you'll do
- Analyze DPU workloads and build system-level power models and rollups.
- Evaluate architectural trade-offs and drive power-saving features and power budgets.
- Correlate pre-silicon estimates with silicon measurements and improve analysis methods.
What they ask for
- Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience.
- Experience in workload analysis and characterization and modeling power-relevant behaviors.
- Experience building system-level power models and rollups through RTL/gate-level power analysis.
- Experience evaluating architectural power-saving features and understanding SoC pipelines and data-movement power trade-offs.
Nice to have
- Experience with low-power implementation flows, power management firmware/software co-design, or post-silicon measurement and correlation.
- Experience with ASIC simulation/emulation and power estimation/sign-off tools.
Pay
$178,000/year to $250,000/year (base salary)
Tools
Python, C/C++, SystemC, FSDB/SAIF, Synopsys PrimePower/PTPX, Cadence Joules, Ansys PowerArtist, UPF
Model-written summary · the original posting is authoritative