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DPU RAS and Debug Architect, Infrastructure Silicon
$178K–$250K
Sunnyvale, CA +2 · Full-time · Posted Oct 5, 2026
- Location
- Sunnyvale, CA
Austin, TX
Menlo Park, CA - Experience
- 8+ years required; 15+ years also stated in the qualifications, without a specified alternative relationship.
- Education
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience; a PhD is also mentioned in the qualifications.
About the job
Architects reliability, availability, serviceability, and debug systems for DPU ASICs, from early design through silicon bring-up.
What you'll do
- Define DPU error detection, correction, reporting, containment, and FIT-rate budgets.
- Design trace, debug, telemetry, and performance-monitoring architectures and hardware/software interfaces.
- Partner with design, DV, PD, and DFT teams on implementation, integration, tradeoffs, and silicon bring-up.
What they ask for
- Bachelor’s degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience.
- 8+ years of relevant industry experience architecting RAS and debug/trace architectures and hardware/software interfaces for NIC/DPU or comparable ASICs.
- Experience with RAS, error-protection mechanisms, memory/interface RAS, error reporting, on-chip debug and trace, performance monitoring, DFT, and relevant standards.
- Experience independently driving analysis and influencing architectural direction through data.
Nice to have
- 15+ years of relevant industry experience architecting RAS and debug/trace architectures for NIC/DPU or comparable ASICs.
- Experience with SystemVerilog or VHDL, ASIC simulation, hyperscale FIT budgets, functional safety, scripting automation, or firmware error-handling flows.
Pay
$178,000/year to $250,000/year (base salary)
Tools
LPDDR/DDR, PCIe, ARM, x86, JTAG, ARM CoreSight, ETM, SystemVerilog
Model-written summary · the original posting is authoritative