Meta
Physical Design Engineer, Reality Labs Silicon
$146K–$209K
Sunnyvale, CA +3 · Full-time · Posted Sep 16, 2026
- Location
- Sunnyvale, CA
Redmond, WA
Austin, TX
San Diego, CA - Experience
- 6+ years in physical design of complex digital ASICs or SoCs; 6+ years in static timing analysis and timing closure.
- Education
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
About the job
Implements and optimizes physical designs for custom silicon used in Meta’s VR and AR products, from floorplanning through tapeout and sign-off.
What you'll do
- Lead physical implementation, timing closure, and physical verification of complex blocks and subsystems.
- Develop physical design methods and power delivery strategies to meet power, performance, and area targets.
- Collaborate with architecture, RTL, verification, and DFT teams; improve implementation flows and automation.
What they ask for
- Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience.
- 6+ years of experience in physical design of complex digital ASICs or SoCs, including floorplanning, placement, CTS, routing, and sign-off.
- 6+ years of experience with static timing analysis and timing closure in advanced process nodes (7nm or below).
- Experience with industry-standard physical design EDA tools and physical verification flows including DRC, LVS, and antenna sign-off.
Nice to have
- Experience with low-power wearable or mobile SoCs, including multi-voltage domains and power gating.
- Experience with Python or Tcl automation, advanced node process design kits (5nm or below), and RTL-to-physical co-design.
Pay
$146,000/year to $209,000/year (base salary)
Tools
Cadence Innovus, Synopsys ICC2, Synopsys Fusion Compiler, FusionPilot/ConfigAI, StarRC, PrimeTime, Python, Tcl
Model-written summary · the original posting is authoritative