Drimva

Micron

Front End Central Product Integration (FE cPIE) MTS (FE)

Boise, ID - ID1 · Full-time · Posted Aug 4, 2026

Experience
7+ years in semiconductor process engineering, process integration, or a related technical role.
Education
Bachelor's, Master's, or PhD degree in a listed engineering or science field, or a related field.

About the job

Leads semiconductor process integration efforts to improve structural uniformity, yield, quality, reliability, and manufacturing performance across technology nodes.

What you'll do

  • Develop and implement solutions for process integration and structural uniformity challenges, using modeling and root-cause analysis.
  • Define and improve inline monitoring and process-control strategies; use data to resolve manufacturing issues and reduce variation.
  • Lead cross-functional and global projects to develop, standardize, and scale integration practices and technology-ramp solutions.

What they ask for

  • Bachelor's, Master's, or PhD degree in Electrical Engineering, Materials Engineering, Materials Science, Physics, Chemical Engineering, or a related field.
  • 7+ years of experience in semiconductor process engineering, process integration, or a related technical role.
  • Strong understanding of semiconductor manufacturing process flows and process interactions.
  • Experience analyzing process changes' impact on yield, device performance, and product reliability; data analysis and structured problem-solving experience; knowledge of DRAM, NAND, or related semiconductor technologies.

Nice to have

  • Experience leading cross-functional technical projects and developing process-control strategies, monitoring systems, or manufacturing best practices.
  • Experience and/or interest in developing Agentic AI workflows into current or future processes.

Tools

DRAM, NAND, Agentic AI

AI focus

Preferred experience and/or interest in developing Agentic AI workflows into current or future processes.

Model-written summary · the original posting is authoritative

First seen Oct 15, 2026 · Last verified Nov 5, 2026 (UTC)