Micron
HBM SoC Physical Design Engineer
Richardson, TX · Full-time · Posted May 7, 2026
- Experience
- Minimum 10 years in a related field.
- Education
- Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
About the job
Implements HBM SoC logic and base-die designs from netlist to GDSII, driving physical design, timing closure, and signoff through tape-out.
What you'll do
- Own block or top-level physical implementation, optimization, timing closure, and physical signoff.
- Integrate complex IP and coordinate with design, DFT, packaging, manufacturing, and related teams to meet PPA and manufacturability goals.
- Support tape-out and post-silicon debug; improve design flows through scripting, automation, and methodology development.
What they ask for
- Strong experience implementing SoC physical designs from netlist to GDSII on advanced nodes and complex designs.
- Proficiency with industry EDA tools such as Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre, or equivalent.
- Solid understanding of STA, clocking, SDC constraints, and timing-closure techniques.
- Experience with power intent and delivery; familiarity with physical verification and signoff concepts including DRC, LVS, and ERC.
Nice to have
- Experience with HBM/DRAM-adjacent or memory-subsystem-heavy SoCs.
- Ability to mentor and develop early-career engineers.
Tools
Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre, SDC, UPF/CPF
Model-written summary · the original posting is authoritative