Micron
HBM SoC Physical Design Engineer
$103K–$210K
Folsom, CA +1 · Full-time · Posted Oct 23, 2026
- Location
- Folsom, CA
Richardson, TX - Experience
- Minimum 3 years of experience in a related field.
- Education
- Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
About the job
Implements HBM SoC logic and base-die designs from netlist to GDSII, driving physical integration, timing closure, and signoff for tape-out.
What you'll do
- Own block or top-level physical implementation, including floor-planning, placement, clock-tree synthesis, routing, and physical optimization.
- Drive timing closure and coordinate physical signoff, resolving DRC/LVS, IR drop/EM, and timing issues.
- Collaborate across design, DFT, packaging, test, and manufacturing teams; support tape-out, post-silicon debug, and flow automation.
What they ask for
- Strong experience implementing SoC physical design from netlist to GDSII on advanced nodes and complex designs.
- Proficiency with industry EDA tools such as Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre, or equivalent.
- Solid understanding of STA, clocking, SDC constraints, and closure techniques.
- Experience with power intent and power delivery considerations; familiarity with physical verification and signoff concepts.
Nice to have
- Experience with HBM/DRAM-adjacent or memory-subsystem-heavy SoCs.
- Good understanding of Agentic AI or willingness to learn it; mentoring experience is also noted.
Pay
$103,000.00 - $210,000.00 USD a year (base salary)
Tools
Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre, STA, SDC, UPF/CPF
AI focus
Help enable and integrate AI-driven tools and AI-enabled workflows into team methodologies; Agentic AI knowledge or willingness to learn is preferred.
Model-written summary · the original posting is authoritative