Micron
HBM SoC Physical Design Engineer
Richardson, TX · Full-time · Posted Oct 28, 2026
- Experience
- Minimum 10 years of experience in a related field.
- Education
- Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
About the job
Implements HBM SoC logic and base-die designs from netlist to GDSII, optimizing PPA and delivering physical signoff for tape-out.
What you'll do
- Own block- or top-level physical implementation, including floor-planning, placement, CTS, routing, optimization, and timing closure.
- Integrate complex IP and coordinate physical verification, power/timing signoff, DFT, packaging, manufacturing, and tape-out activities.
- Improve implementation flows through scripting, automation, and methodology development, including LLMs.
What they ask for
- Strong experience implementing complex SoC physical designs from netlist to GDSII on advanced nodes.
- Proficiency with industry EDA tools such as Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre, or equivalent.
- Knowledge of STA, clocking, SDC constraints, and common timing-closure techniques.
- Experience with power intent and delivery considerations, and familiarity with physical verification/signoff including DRC, LVS, and ERC.
Nice to have
- Experience with HBM / DRAM-adjacent or memory-subsystem-heavy SoCs.
- Ability to mentor and develop early-career engineers.
Tools
Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre, SDC, UPF/CPF, LLM's
AI focus
Use scripting and automation, including LLMs, to improve productivity and develop implementation methodologies.
Model-written summary · the original posting is authoritative