Micron
HBM SoC Physical Design Engineer
Richardson, TX · Full-time · Posted Jun 5, 2026
- Experience
- Minimum 10 years in a related field.
- Education
- Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
About the job
Implements HBM SoC logic and base-die designs from netlist to GDSII, optimizing PPA and completing physical signoff for tape-out.
What you'll do
- Own block or top-level physical implementation, including floor-planning, placement, CTS, routing, and optimization.
- Drive timing closure and coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff.
- Support tape-out, cross-functional integration, post-silicon debug, and improvements to implementation flows.
What they ask for
- Strong SoC physical-design implementation experience from netlist to GDSII on advanced nodes and complex designs.
- Proficiency with industry EDA tools such as Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre, or equivalent.
- Solid understanding of STA, clocking, SDC constraints, and closure techniques.
- Experience with power intent and delivery, plus familiarity with physical verification and signoff concepts.
Nice to have
- Experience with HBM/DRAM-adjacent or memory-subsystem-heavy SoCs.
- Ability to mentor and develop early-career engineers.
Tools
Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre, SDC, UPF/CPF
AI focus
The posting encourages candidates to use AI tools to enhance resumes or application materials, while requiring information to remain accurate; the role itself does not involve AI work.
Model-written summary · the original posting is authoritative