Micron
HBM SoC RTL Design Engineer
$121K–$247K
Folsom, CA · Full-time · Posted Jul 31, 2026
- Experience
- Minimum of 3 years of experience in a related field.
- Education
- Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
About the job
Design and integrate RTL for next-generation HBM SoC logic-die blocks, collaborating across teams to meet performance, power, area, and schedule goals.
What you'll do
- Design RTL for SoC-level blocks and subsystems; integrate internal and third-party IP.
- Translate architectural specifications into RTL and support SoC integration, including clocking, reset, power intent, and configuration.
- Assist with pre-silicon validation, post-silicon bring-up, and silicon issue root-cause analysis.
What they ask for
- Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
- Proficiency in SystemVerilog/Verilog and familiarity with SoC integration methodologies.
- Experience with the RTL-to-GDS flow, including synthesis and static timing analysis.
- Familiarity with EDA tools from Cadence, Synopsys, and/or Siemens; programming or scripting experience.
Nice to have
- Experience with HBM, DRAM, or memory-centric SoC designs.
- Exposure to DFT, hardware emulation or acceleration platforms, or Agentic AI.
Pay
$121,000.00 - $247,000.00 USD a year (base salary)
Tools
SystemVerilog/Verilog, Cadence, Synopsys, Siemens, Python, TCL, Perl, shell scripting
AI focus
Enable and integrate AI-driven tools and AI-enabled workflows into team methodologies; Agentic AI familiarity or willingness to learn is preferred.
Model-written summary · the original posting is authoritative