Micron
HBM SoC RTL Design Engineer
$121K–$247K
Folsom, CA +1 · Full-time · Posted Sep 21, 2026
- Location
- Folsom, CA
Richardson, TX - Experience
- Minimum of 6 years in a related field.
- Education
- Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
About the job
Design, integrate, and validate RTL for next-generation HBM SoC logic-die blocks and subsystems, while helping integrate AI-enabled workflows into team methodologies.
What you'll do
- Design and implement SoC-level RTL; integrate internal and third-party IP.
- Support SoC integration, pre-silicon validation, post-silicon bring-up, and silicon issue analysis.
- Collaborate across engineering teams and contribute to specifications, documentation, and design reviews.
What they ask for
- Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
- Proficiency in SystemVerilog/Verilog and familiarity with SoC integration methodologies.
- Experience with the RTL-to-GDS flow, including synthesis and static timing analysis.
- Familiarity with EDA tools from Cadence, Synopsys, and/or Siemens; programming or scripting experience.
Nice to have
- Experience with HBM, DRAM, or memory-centric SoC designs; familiarity with high-speed interfaces, clocking, reset, or power management.
- Exposure to DFT or hardware emulation/acceleration; understanding of or willingness to learn Agentic AI.
Pay
$121,000.00 - $247,000.00 a year USD base salary
Tools
SystemVerilog, Verilog, Cadence, Synopsys, Siemens, Python, TCL, Perl
AI focus
Enable and integrate AI-driven tools and AI-enabled workflows into team methodologies; Agentic AI experience or willingness to learn is preferred.
Model-written summary · the original posting is authoritative