Drimva

Micron

High Bandwidth Memory Design Architect - E1 to SMTS

Richardson, TX · Full-time · Posted Oct 28, 2026

Experience
Experience developing engineering models, simulations, or analytical methodologies; job experience or university-related work accepted. No years specified.
Education
Degree in Electrical Engineering, Computer Engineering, or a related field.

About the job

Analyze and model future HBM and DRAM architectures, evaluate design tradeoffs, and support technology pathfinding with multidisciplinary engineering teams.

What you'll do

  • Use models, simulations, silicon data, and AI-assisted techniques to evaluate architecture performance and design tradeoffs.
  • Develop modeling and data-analysis methods, validate assumptions, and make evidence-based design recommendations.
  • Collaborate across engineering teams and communicate findings in reviews, presentations, and documentation.

What they ask for

  • Degree in Electrical Engineering, Computer Engineering, or a related field completed before employment starts.
  • Strong foundation in at least two listed areas, including CMOS circuits, computer architecture, memory systems, signal integrity, or advanced packaging.
  • Experience developing engineering models, simulations, or analytical methods through job experience or university-related work.
  • Ability to analyze complex technical problems and communicate recommendations effectively.

Nice to have

  • Experience or research related to HBM, DRAM, SRAM, memory controllers, high-speed interfaces, semiconductor architecture, or 3D integration.
  • Experience with circuit-design simulation tools, data analytics, AI, LLMs, or Generative AI for engineering analysis.

Tools

HSPICE, FineSim, Spectre, AI, Large Language Models (LLMs), Generative AI

AI focus

Use AI-assisted techniques, data analytics, LLMs, or Generative AI to accelerate architecture exploration, engineering productivity, and technical analysis.

Model-written summary · the original posting is authoritative

First seen Oct 29, 2026 · Last verified Nov 5, 2026 (UTC)