Intern – DRAM Technology Physical Design and Block-Level PPA Optimization

What you'll do

• Implement logic blocks through floorplanning, placement, clock tree synthesis, routing, and PPA optimization.
• Benchmark PPA across libraries and block configurations; perform static timing analysis and support timing closure.
• Run physical verification, including DRC, LVS, and IR-drop analysis, and use AI tools to automate PPA workflows.

What they ask for

• Currently pursuing a B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related technical field.
• Demonstrated understanding of VLSI design, CMOS circuits, digital logic, and the ASIC physical design flow.
• Coursework, research, or project experience with scripting languages such as Python, Perl, or TCL.
• Expected graduation date of Fall 2025 or later.

Nice to have

• Hands-on experience with place-and-route tools such as Synopsys ICC2 or Cadence Innovus, and exposure to timing analysis tools such as PrimeTime or Tempus.
• Knowledge of SDC, LEF/DEF, low-power design (UPF or CPF), or AI-assisted engineering automation.

Tools

Python, Perl, TCL, Synopsys ICC2, Cadence Innovus, PrimeTime, Tempus, UPF

AI focus

Uses Generative AI, AI Assistants, and Agentic AI to automate data collection, reporting, comparison, and PPA workflow optimization.