Micron
MTS - HIG HBM - ARCHITECTURE
Richardson, TX · Full-time · Posted Oct 14, 2026
- Experience
- 10+ years of relevant Engineering or Design Engineering experience on high-speed IO, PLL, Tx, Rx, Equalization, clock tree.
- Education
- MS or PhD in EE
About the job
Designs and optimizes HBM high-speed IO and TSV IO architecture, modeling, and analysis across product development, including simulation-to-silicon feedback.
What you'll do
- Define HBM IO architecture, performance targets, and design quality processes and requirements.
- Develop IO and TSV modeling methodologies for architecture tradeoffs, SI/PI evaluation, and optimization.
- Correlate simulations with silicon results and use AI-assisted analytics to identify root causes in silicon data.
What they ask for
- Good IO circuit design background, including analog and digital design and simulation experience.
- Experience with circuit verification and optimization, including layout verification and parasitic extraction.
- MS or PhD in EE.
- Familiarity with one or more high-speed interfaces such as HBM, DDR, UCIe, PCIe, or MIPI.
Nice to have
- Prior circuit-debug experience through Product Engineering or equivalent.
- Knowledge of advanced packaging environments (CoWoS, HBM stack, D2D, etc.).
Tools
HBM, TSV IO, SI, PI, CoWoS, D2D, DDR, UCIe
AI focus
Use AI-assisted analytics to accelerate root-cause identification from complex, multivariable silicon data.
Model-written summary · the original posting is authoritative