Drimva

Micron

New College Grad - HBM SoC Design Engineer/Architect

$79K–$175K

Folsom, CA +1 · Full-time · Posted Sep 29, 2026

Location
Folsom, CA
Richardson, TX
Experience
No specific number of years stated; relevant academic, research, internship, or project experience is required.
Education
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. Master's or Ph.D. preferred.

About the job

Design, integrate, and validate digital logic and memory-centric SoCs for next-generation HBM solutions.

What you'll do

  • Design and integrate digital logic and subsystem RTL for HBM SoCs.
  • Collaborate across engineering teams to translate requirements into microarchitectures, interfaces, and implementation plans.
  • Support design-quality analysis and evaluate power, performance, area, and timing tradeoffs; develop automation and AI-assisted workflows.

What they ask for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, completed before employment starts.
  • Academic, research, internship, or project experience in digital design, ASIC development, FPGA design, computer architecture, or a related discipline.
  • Working knowledge of Verilog, SystemVerilog, VHDL, or another hardware description language.
  • Understanding of digital design fundamentals, including FSMs, pipelining, clocking, reset strategies, timing, and synchronous logic.

Nice to have

  • Master's or Ph.D. in a related technical discipline; experience in SoC design, RTL development, verification, physical design, embedded systems, or semiconductor technologies.
  • Familiarity with synthesis, STA, simulation, formal verification, UVM, FPGA prototyping, EDA tools, memory systems, high-speed interfaces, or AI-enabled engineering tools.

Pay

$79,000.00 - $175,000.00 a year (base salary; USD)

Tools

Verilog, SystemVerilog, VHDL, UVM, HBM, DDR, LPDDR, PCIe

AI focus

Develop automation and use AI-assisted workflows, Generative AI, LLMs, or Agentic AI to improve engineering productivity, verification efficiency, and design analysis.

Model-written summary · the original posting is authoritative

First seen Oct 16, 2026 · Last verified Nov 5, 2026 (UTC)