Principal Analog Design Engineer — Mixed-Signal PHY (Clocking / High-Speed I/O)

What you'll do

• Lead development of clocking, transmitter, and receiver circuits and contribute to top-level PHY analog architecture.
• Build transistor-level simulation testbenches and assess process corners, statistical variation, build margin, and yield sensitivity.
• Define analog-to-digital interface specifications, guide custom layout, and support lab characterization after silicon fabrication.

What they ask for

• BS, MS, or PhD in Electrical Engineering or a related field, or equivalent experience.
• 10+ years of analog/mixed-signal IC build experience, including at least one tape-out as a primary circuit owner.
• Deep expertise in PLL, DLL, or CDR architecture and transistor-level implementation in sophisticated CMOS nodes.
• Strong HSpice or equivalent simulation skills, jitter-analysis knowledge, and ability to use AI/ML/LLMs for productivity and efficiency.

Nice to have

• High-speed transmitter or receiver development, or familiarity with die-to-die PHY architectures such as UCIe, AIB, or BoW.
• Experience with OTP/fuse-based calibration or post-silicon characterization.

Tools

PLL, DLL, CDR, HSpice, UCIe, AIB, BoW, CTLE/DFE

AI focus

Use AI/ML/LLMs for productivity and efficiency.