Micron
Principal ASIC Design Engineer
$186K–$407K
Boise, ID - Main Site +3 · Principal · Full-time · Posted Sep 24, 2026
- Location
- Boise, ID - Main Site
Folsom, CA
Richardson, TX
San Jose, CA - Experience
- 7–12 years of ASIC design experience, with at least one complete front-to-back tape-out.
- Education
- BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field.
About the job
Own digital architecture and RTL design for high-speed interface test ASICs, from specification through synthesis, timing closure, and handoff to physical implementation.
What you'll do
- Architect and implement synthesizable digital blocks, define CDC strategy, and coordinate chip integration with analog and layout teams.
- Run synthesis and static timing analysis; provide constraints, netlists, and design guidance to physical implementation teams.
- Self-verify RTL, support verification and DFT planning, and maintain design and implementation documentation.
What they ask for
- BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field.
- Proficiency in synthesizable SystemVerilog RTL design.
- Hands-on logic synthesis and static timing analysis experience using the specified tool options.
- RTL simulation/debug proficiency and understanding of CDC analysis methodologies.
Nice to have
- Experience with custom mixed-signal design teams and PHY-adjacent implementation.
- Experience with place-and-route and physical verification sign-off.
Pay
$186,000.00 - $407,000.00 a year USD (base salary)
Tools
SystemVerilog, Synopsys Design Compiler, Cadence Genus, PrimeTime, Tempus, VCS, Xcelium, SpyGlass
AI focus
Use AI tools to improve productivity across design, debug, and documentation workflows.
Model-written summary · the original posting is authoritative