Principal Compute Pathfinding ASIC Design

What you'll do

• Define ASIC and system architectures, specifications, logic partitioning, interfaces, and design tradeoffs.
• Oversee logic design and synthesis, and evaluate physical design impacts including placement, routing, timing, and power.
• Model and validate system-level designs, assess complete ASIC flows, and collaborate on implementation readiness and technology roadmaps.

What they ask for

• Master’s degree in Electrical or Computer Engineering, or a Bachelor’s degree (or equivalent experience) with 12+ years of relevant ASIC architecture and build experience.
• Extensive experience with Verilog/SystemVerilog for architecture exploration, logic design, and RTL definition.
• Strong background in computer architecture, data processing, and system-level design concepts.
• Experience across ASIC design flows, including logic design, synthesis, and interaction with physical design teams.

Nice to have

• Experience with advanced ASIC design tools and methodologies, including synthesis, static timing analysis, and power optimization.
• Familiarity with high-level synthesis (HLS), system modeling, or architectural exploration frameworks.

Pay

$168,000.00 - $374,000.00 USD a year (base salary)

Tools

Verilog, SystemVerilog, synthesis, static timing analysis, high-level synthesis (HLS), place-and-route