Principal Design Engineer

What you'll do

• Design and verify major IO/datapath blocks to meet performance specifications, using AI to accelerate exploration, sizing, and verification.
• Champion AI adoption by evaluating tools, running pilots, and publishing methodologies that improve cycle time or quality.
• Collaborate with integration, design, and Apps teams on interfaces and specifications; document AI-augmented methods and mentor engineers.

What they ask for

• BS/MS in Electrical Engineering with 8+ years of IC design experience.
• Hands-on use of AI tools with concrete examples of productivity or design impact.
• Experience redesigning workflows around AI, including restructuring specs, reviews, or verification and building prompts or agents.
• Deep understanding of high-speed IO performance, power/area optimization, chip architecture/floor planning, physical design flows, layout optimization, and parasitic extraction.

Nice to have

• Built or deployed custom AI agents, LLM pipelines, or ML models for IC design, verification, layout, or debug; familiarity with prompt engineering, RAG, fine-tuning, or agentic frameworks.
• DRAM interface experience (DDR4/5, LPDDR5/6, HBM3/4) or other high-speed standards; deep knowledge of CMOS device physics, reliability, BSIM modeling, and IO targets.

Pay

$176,000.00 - $298,000.00 a year (USD, base salary)

Tools

LLMs, code/RTL generation, spec parsing, waveform interpretation, layout engines, ML-based EDA, RAG, BSIM

AI focus

AI-first engineering: use and lead adoption of AI tools for IC design, automation, specification and verification workflows, and engineering productivity.