Micron
Principal Design Engineer
$181K–$308K
San Jose, CA · Principal · Full-time · Posted Oct 20, 2026
- Experience
- 8+ years in memory datapath, SRAM, or high-speed custom design.
- Education
- BS/MS in EE or related field.
About the job
Leads NAND datapath architecture and design between the page buffer and IO, using AI-assisted workflows and advancing timing closure, verification, and semi-custom design methods.
What you'll do
- Define, design, and verify NAND datapath blocks, including wave-pipelined buses, FIFOs, sensing, repair, and clocking.
- Close timing and coordinate physical co-design, including floorplanning, routing, and post-layout timing correlation.
- Use AI to accelerate design and verification, automate checks, establish workflows, and guide technical direction and mentoring.
What they ask for
- BS/MS in EE or a related field.
- Deep expertise in flop-to-flop and wave-pipelined timing closure.
- Experience designing sense amps, datalines, or SRAM read/write, including Monte Carlo/high-sigma verification.
- Daily hands-on AI use with concrete examples of improved productivity or design outcomes; proven layout collaboration on floorplanning, extraction, and post-layout timing correlation.
Nice to have
- NAND/DRAM/SRAM periphery experience; memory repair and redundancy design.
- AI agents, LLM/RAG pipelines, or ML models for IC design, verification, or debug.
Pay
$181,000.00 - $308,000.00 a year (USD, base salary)
Tools
RTL, SPICE, SDC/STA, synthesis/APR/ECO, Monte Carlo, LLM/RAG
AI focus
Use AI daily for RTL generation, scripting, timing and waveform analysis, and agents that automate timing, Monte Carlo, and repair-coverage checks; champion AI adoption and standard workflows.
Model-written summary · the original posting is authoritative