Principal Engineer - HIG Component Validation

What you'll do

• Define architecture-aware validation strategies, coverage direction, and testability requirements for HBM products.
• Prepare validation strategies, test environments, and execution plans before first silicon; identify risks and improve debug efficiency.
• Lead investigations of architecture, building, and silicon issues, collaborating across engineering and systems teams and promoting AI-enabled validation methods.

What they ask for

• Bachelor’s or Master’s degree or equivalent experience in Electrical Engineering, Computer Engineering, or a related field.
• Proven expertise debugging DRAM/HBM issues pre-silicon and post-silicon.
• Experience analyzing schematics and conducting timing-accurate SPICE-level or transistor-level simulations.
• Experience with Verilog/SystemVerilog, Python, Linux, and version control systems (git, svn, Perforce).

Nice to have

• Experience defining validation strategy or coverage methodology for HBM or advanced DRAM products.
• Experience with design-for-validation/testability, validation hardware, lab equipment, high-speed I/O, signal integrity, or AI/ML and generative-AI solutions for validation, test, or debug.

Tools

Verilog/SystemVerilog, Python, Linux, git, svn, Perforce, SPICE

AI focus

Develop and promote AI-enabled validation methodologies; preferred experience includes defining or applying AI/ML or generative-AI solutions to validation, test, or debug workflows.