Micron
Principal, MTS, DRAM Systems Architect
Boise, ID - Main Site · Principal · Full-time · Posted Jul 22, 2026
- Experience
- Minimum MSEE + 10 years or BSEE + 12 years of industry experience.
- Education
- MSEE or BSEE.
About the job
Designs, verifies, optimizes, and supports high-speed IO and clocking circuits for Micron DRAM products, including analysis of signal impairments and their impact on system timing.
What you'll do
- Design, optimize, and verify high-speed IO and clocking circuits; evaluate timing and jitter sensitivity at circuit and full-chip levels.
- Develop modeling, analysis, and simulation methods to assess circuit performance and its impact on product specifications.
- Correlate silicon performance with simulations and collaborate on process development and AI-assisted design-flow improvements.
What they ask for
- MSEE with 10 years or BSEE with 12 years of industry experience in high-speed IO, timing, and clocking circuit design, with proven silicon successes.
- Ability to supervise layout work and understand layout practices that minimize parasitic impacts.
- Strong interpersonal and communication skills for conveying technical concepts.
- Ability to multitask across product teams and silicon-validation efforts.
Nice to have
- DRAM circuit design; channel modeling, characterization, noise and timing-budget analysis, equalization, or signal integrity.
- Device physics, CMOS processing, mentoring, AI/ML usage, PERL/Python scripting, or Agentic AI.
Tools
PERL, Python
AI focus
Work with data science and EDA teams to leverage and improve AI-assisted design flows and circuit optimization; AI/ML usage and Agentic AI are preferred.
Model-written summary · the original posting is authoritative