Micron
PRINCIPAL RTL DESIGN
Boise, ID - Main Site · Principal · Full-time · Posted Aug 3, 2026
- Experience
- Master’s degree with 8+ years of experience, or Bachelor’s degree with 10+ years of pre-silicon RTL design experience.
- Education
- Master’s degree in Electrical Engineering or Bachelor’s degree.
About the job
Leads the full RTL design lifecycle for DRAM digital and mixed-signal IP, from architecture and implementation through silicon-ready signoff, meeting PPA targets.
What you'll do
- Own RTL design from specification through signoff and handoff.
- Architect efficient designs and complete front-end checks, including lint, CDC/RDC, synthesis, UPF, and timing QoR.
- Collaborate across teams on timing closure and PPA, and improve design methodologies and flows.
What they ask for
- Proven ownership of complex RTL/IP development from micro-architecture through physical-design handoff.
- Strong ASIC low-power design experience, including UPF-based power intent and power-aware CDC/RDC.
- In-depth knowledge of RTL design, logic synthesis, functional verification, and static timing analysis (STA).
- Proficiency in Verilog/SystemVerilog and industry-standard simulation and front-end tools.
Nice to have
- Background in DRAM or other memory architectures.
- Experience with complex digital logic or mixed-signal interfacing; familiarity with CMOS digital and analog-integrated circuit concepts.
Tools
Verilog/SystemVerilog, UPF, CDC/RDC, STA
Model-written summary · the original posting is authoritative