Micron
Principal, SMTS, DRAM Systems Architect
Boise, ID - Main Site · Principal · Full-time · Posted Jul 22, 2026
- Experience
- 10 years with an MSEE, or 12 years with a BSEE.
- Education
- MSEE or BSEE.
About the job
Architects, designs, optimizes, verifies, and supports high-speed IO and clocking circuits for Micron DRAM products.
What you'll do
- Define, design, optimize, and verify high-speed IO and clocking circuits, including timing and jitter performance.
- Develop modeling, analysis, and simulation methods to assess circuit performance and its impact on product specifications.
- Compare silicon performance with simulations and collaborate on correlation, process integration, and transistor modeling.
What they ask for
- MSEE and 10 years, or BSEE and 12 years, of industry experience in high-speed IO, timing, and clocking circuit design, with proven silicon successes.
- Ability to supervise layout work and understand high-speed circuit layout practices.
- Strong written and verbal communication skills.
- Demonstrated ability to mentor and coach early-career engineers.
Nice to have
- DRAM circuit design; channel modeling and characterization; transceiver noise and timing budget analysis; equalization; or SI knowledge.
- Understanding of device physics and basic CMOS processing; AI/ML usage and scripting in PERL/Python; use of Agentic AI.
Tools
PERL, Python
AI focus
Preferred qualifications include demonstrated AI/ML usage and use of Agentic AI.
Model-written summary · the original posting is authoritative