Senior CAD Engineer - Layout/Verification/Simulation

What you'll do

• Develop, integrate, evaluate, and qualify CAD tools and production flows; debug workflow and tool-integration issues.
• Improve tools and flows, provide end-user training and support, and mentor engineers.
• Lead technical projects and apply AI/ML and agentic AI to CAD automation, debugging, and user support.

What they ask for

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent.
• 5+ years of industry experience in CAD, EDA, or semiconductor design.
• Experience developing or supporting EDA tools and flows in custom layout, physical verification, circuit simulation, or digital implementation; experience with IC design CAD tools.
• Proficiency in Python and at least one additional listed language, plus Linux/Unix and shell scripting; solid CMOS and VLSI fundamentals.

Nice to have

• Experience with Cadence Virtuoso and SKILL, Calibre DRC/LVS or SVRF, circuit simulators, RTL-to-GDS tools, or parasitic extraction tools.
• Experience applying AI/ML, large language models, or agentic AI to engineering workflows; source control, automated testing, release management, or memory development knowledge.

Pay

USD $104,000.00 - $221,000.00 a year (base salary)

Tools

Python, SKILL, Tcl, Perl, C, C++, Linux/Unix, shell scripting

AI focus

Apply AI/ML and agentic AI to CAD automation, debugging, and user support; AI/ML, large language models, or agentic AI experience is preferred.