Drimva

Micron

Senior / Principal DRAM Product Development Engineer – DEG Technology

Boise, ID - Main Site · Principal · Full-time · Posted Oct 12, 2026

Experience
2–5 years of relevant experience for Senior-level candidates or 8+ years of relevant experience for Principal-level candidates.
Education
Bachelor’s degree in Electrical Engineering, Computer Engineering, Physics with an emphasis in semiconductor electronics, or an equivalent field.

About the job

Designs and optimizes DRAM circuitry while supporting process-node development, silicon bring-up, yield improvement, and production ramp.

What you'll do

  • Design, analyze, verify, and optimize DRAM circuits, including Sense Amplifiers, timing distribution, calibration, and training features.
  • Develop circuit- or architecture-level solutions to improve robustness, performance, scalability, and yield; support process qualification, silicon bring-up, and production ramp.
  • Lead technical investigations and cross-functional initiatives, guide layout and modeling work, document findings, and mentor junior engineers.

What they ask for

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, Physics with an emphasis in semiconductor electronics, or an equivalent field.
  • Experience with DRAM, NAND, logic, or related interfaces.
  • Experience with circuit design, modeling, simulation, design verification, or silicon validation using relevant CAD tools.

Nice to have

  • Master’s degree in Electrical Engineering, Computer Engineering, Physics with an emphasis in semiconductor electronics, or an equivalent field.
  • Experience with AI-assisted analytics or Agentic AI tools for design, verification, data interpretation, anomaly detection, or yield improvement.

Tools

DRAM, NAND, CAD tools, CMOS, BSIM

AI focus

Preferred experience using AI-assisted analytics for data interpretation, anomaly detection, and yield improvement, and Agentic AI tools for design and verification.

Model-written summary · the original posting is authoritative

First seen Oct 15, 2026 · Last verified Nov 5, 2026 (UTC)