Senior/Staff/Principal Package Design Engineer

What you'll do

• Partner with silicon, business, customer, and architecture teams to define product concepts and optimize die floorplans, interconnections, and package architecture.
• Lead package floorplanning, routing, layout, stack-up and interconnect definition, and manufacturing documentation.
• Work with SI/PI teams, OSAT partners, suppliers, and development teams on design validation, manufacturability, DFMEA, and HVM readiness.

What they ask for

• Bachelor’s degree in Electrical Engineering, Mechanical Engineering, Materials Science, or a related field plus 5 years of semiconductor package design experience; OR a master’s degree in those fields plus 3 years of experience.
• Hands-on proficiency with advanced package EDA tools such as Cadence Allegro Package Designer+, Cadence Integrity 3D-IC, or Siemens/Mentor Xpedition.
• Experience with flip chip and wire bond interconnects, BEOL/RDL flows, substrate stack-ups, and high-density routing.
• Experience partnering with SI/PI simulation teams and collaborating with OSAT or assembly engineering organizations to deliver designs through HVM.

Nice to have

• 7 plus years of experience with advanced DRAM technologies such as LPDDR, HBM, or GDDR.
• Experience with TSV stacking, micro-bump layout, CPI analysis, 2.5D/3D-IC, FOWLP, SiP, or package drawings using AutoCAD / Autodesk Mechanical.

Tools

Cadence Allegro Package Designer+, Cadence Integrity 3D-IC, Siemens/Mentor Xpedition, LPDDR, HBM, GDDR, AutoCAD / Autodesk Mechanical, BEOL/RDL

AI focus

Preferred experience and/or interest in developing Agentic AI workflows into current or future processes.