Drimva

Micron

SoC Physical Verification Engineer, HBM

$97K–$205K

Folsom, CA +1 · Full-time · Posted Aug 28, 2026

Location
Folsom, CA
Richardson, TX
Experience
2 or more years of relevant industry experience (listed in preferred qualifications).
Education
Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.

About the job

Own physical-verification sign-off for next-generation HBM logic dies and memory-centric SoCs, from layout through tape-out and silicon bring-up.

What you'll do

  • Execute and close full-chip and hierarchical verification, including DRC, LVS, ERC, PERC, antenna, DFM, reliability, density, metal-fill, and CMP checks.
  • Develop and optimize verification rule decks, flows, automation, and regression infrastructure; perform parasitic RC extraction and support correlation with silicon measurements.
  • Collaborate across design, CAD, product engineering, EDA, and foundry teams, and drive adoption of AI/ML tools and AI-assisted workflows.

What they ask for

  • Experience with full-chip or block-level physical verification for advanced-node SoC, memory, or heterogeneous-integration designs.
  • Experience with DRC, LVS, ERC, PERC, DFM, antenna, and reliability sign-off methodologies.
  • Experience with tools such as Calibre, IC Validator (ICV), Pegasus, or similar, including rule-deck development or customization.
  • Working knowledge of RTL-to-GDS flows, including place-and-route and extraction; proficiency demonstrating AI and AI-enabled development workflows.

Nice to have

  • HBM, DRAM, memory-centric SoC, multi-die, chiplet, or 2.5D/3D integration experience.
  • GPU, CPU, or accelerator implementation experience; foundry rules and manufacturability familiarity; or post-silicon analysis and yield-learning exposure.

Pay

$97,000.00 - $205,000.00 a year (USD; base salary)

Tools

Calibre, IC Validator (ICV), Pegasus, Python, Tcl, Perl, TSMC

AI focus

Drive adoption of machine-learning and AI-based physical-verification and PPA-optimization tools, and demonstrate AI-assisted development workflows.

Model-written summary · the original posting is authoritative

First seen Oct 15, 2026 · Last verified Nov 5, 2026 (UTC)