Drimva

Micron

Sr Design Verification Engineer, DRAM

Boise, ID - Main Site · Senior · Full-time · Posted Aug 25, 2026

Experience
4+ years of semiconductor design, verification, or development experience. Preferred: 5+ years in design verification, parasitic modeling, or mixed-signal design.
Education
Bachelor’s degree in Electrical Engineering or a related field; preferred: Master’s degree in Electrical Engineering or a related field.

About the job

Verifies and optimizes digital and analog circuit designs for next-generation DRAM products through modeling, simulation, debug, and silicon validation.

What you'll do

  • Verify circuit functionality, reliability, power, and compliance with product specifications; drive verification planning, coverage closure, and debug.
  • Model and simulate circuits, identify design improvements, and support silicon validation, reticle experiments, and tape-out.
  • Collaborate with engineering, manufacturing, and product teams to deliver manufacturable memory designs.

What they ask for

  • Bachelor’s degree in Electrical Engineering or a related field.
  • 4+ years of semiconductor design, verification, or development experience.
  • Experience with verification planning, coverage strategies, debug, and silicon correlation.
  • Experience modeling and simulating integrated circuits using SPICE and Verilog; knowledge of digital and analog circuit methodologies and tools such as Synopsys and Cadence Virtuoso.

Nice to have

  • Master’s degree in Electrical Engineering or a related field; experience with UVM, mixed-signal verification, advanced DRAM architectures, or DDR5+ methodology development.
  • Knowledge of advanced memory technologies; 5+ years in design verification, parasitic modeling, or mixed-signal design; Python and AI-assisted or agentic AI tools for verification and EDA automation.

Tools

SPICE, Verilog, Synopsys, Cadence Virtuoso, UVM, Python

AI focus

Preferred use of AI-assisted or agentic AI tools to improve design verification and EDA automation workflows.

Model-written summary · the original posting is authoritative

First seen Oct 15, 2026 · Last verified Nov 5, 2026 (UTC)