Sr Digital Design Engineer

What you'll do

• Develop RTL and perform front-end checks, synthesis, timing analysis, and timing closure.
• Optimize power, performance, area, and design quality with architecture, verification, and physical design teams.
• Improve design methodologies, automation, and RTL-to-GDS flows.

What they ask for

• Master’s degree in Electrical Engineering (or equivalent) with 4+ years of experience, or Bachelor’s degree with 5+ years of experience in digital ASIC/RTL design.
• Experience developing complex RTL from specification through implementation handoff.
• Knowledge of ASIC front-end flows, including functional verification, logic synthesis, CDC/RDC analysis, and STA; experience with SDC constraints and multi-mode multi-corner timing.
• Proficiency with Verilog/SystemVerilog and industry-standard simulation tools; experience with low-power methodologies, UPF-based power intent, and PPA optimization.

Nice to have

• RTL experience with memory products or other high-performance digital designs; familiarity with CMOS digital and mixed-signal circuit concepts.
• Experience with cross-functional collaboration and improving productivity through process improvements, automation, or enhanced design methodologies.

Tools

Verilog, SystemVerilog, SDC, UPF, CDC/RDC, STA, RTL-to-GDS

AI focus

Preferred ability to demonstrate AI-assisted technologies and generative AI tools to improve engineering efficiency and collaboration.