Drimva

Micron

Sr Digital Design Engineer

Boise, ID - Main Site · Senior · Full-time · Posted Aug 14, 2026

Experience
Master’s degree in Electrical Engineering (or equivalent) with 4+ years of experience, or Bachelor’s degree with 5+ years of experience in digital ASIC/RTL design.
Education
Master’s degree in Electrical Engineering (or equivalent), or Bachelor’s degree.

About the job

Designs and delivers digital and mixed-signal DRAM blocks through the RTL-to-GDS flow, optimizing design quality, power, performance, and area.

What you'll do

  • Develop RTL for complex DRAM digital and mixed-signal blocks and carry designs from specification toward implementation handoff.
  • Perform front-end checks and analysis, including linting, CDC/RDC, synthesis, timing constraints, and timing closure.
  • Collaborate across architecture, verification, and physical design teams; improve design methodologies, automation, and RTL-to-GDS flows.

What they ask for

  • Proven experience developing RTL for complex digital designs from specification through implementation handoff.
  • Knowledge of ASIC front-end flows, including RTL design, functional verification, logic synthesis, CDC/RDC analysis, and STA.
  • Experience developing SDC constraints and handling multi-mode, multi-corner timing scenarios.
  • Proficiency with Verilog/SystemVerilog and industry-standard simulation tools; experience with low-power methodologies, UPF, and PPA optimization.

Nice to have

  • RTL experience for memory products or other high-performance digital designs; familiarity with CMOS digital and mixed-signal concepts.
  • Experience improving engineering productivity through process improvements, automation, or enhanced design methodologies.

Tools

Verilog, SystemVerilog, SDC, UPF, RTL-to-GDS, CDC/RDC, STA

AI focus

Encouraged to demonstrate AI-assisted technologies and generative AI tools to improve engineering efficiency and collaboration.

Model-written summary · the original posting is authoritative

First seen Oct 15, 2026 · Last verified Nov 4, 2026 (UTC)