Micron
Sr. Member Technical Staff - ESD and Latch-Up - HBM
$177K–$334K
Folsom, CA · Staff · Full-time · Posted Aug 5, 2026
- Experience
- 10+ years of experience in ESD and latch-up design and reliability.
- Education
- MS or PhD in Electrical Engineering or related field, or equivalent practical experience.
About the job
Defines ESD and latch-up protection architecture for next-generation HBM products, from early design through silicon validation, to improve product reliability.
What you'll do
- Define end-to-end ESD and latch-up architecture and protection strategies for HBM dies, high-speed I/O, TSV interfaces, and advanced packaging.
- Establish ESD/LUP standards, rule decks, and signoff criteria; correlate design assumptions with silicon validation and field reliability.
- Partner with foundry and packaging teams to address system-level ESD challenges.
What they ask for
- MS or PhD in Electrical Engineering or related field, or equivalent practical experience.
- 10+ years of experience in ESD and latch-up design and reliability.
- Expertise in advanced CMOS technologies such as FinFET or GAA.
- Experience with 3D IC, TSV, or die-to-die interfaces.
Nice to have
- Experience defining architecture across multi-die or stacked memory systems; background in ESD device or circuit design.
- Experience developing PDK collateral or ESD rule decks; experience debugging silicon failures related to ESD or latch-up; demonstrated technical leadership across cross-functional teams.
Pay
$177,000.00 - $334,000.00 a year USD (base salary)
Tools
FinFET, GAA, 3D IC, TSV, PDK
AI focus
Supports the design and deployment of AI-enabled solutions to improve efficiency and decision-making.
Model-written summary · the original posting is authoritative