Micron
Staff Digital Physical Implementation and Integration Engineer
$145K–$246K
San Jose, CA · Staff · Full-time · Posted Aug 18, 2026
- Experience
- 5+ years of digital physical design, including at least one full tapeout owned end-to-end.
- Education
- Bachelor’s degree in Computer Engineering or Electrical Engineering
About the job
Own physical implementation and top-level integration of large digital NAND designs, from planning and block-level APR through full-chip timing, physical-verification, and sign-off closure.
What you'll do
- Plan and integrate top-level partitions, including placement, routing, constraints, pin optimization, and assembly.
- Run block-level APR and STA; close timing, DRC, LVS, EM/IR, antenna, and ECO issues.
- Automate design flows and collaborate with STA, DFT, CAD, and layout teams on methodology and integration.
What they ask for
- Bachelor’s degree in Computer Engineering or Electrical Engineering.
- Strong static timing analysis and debug skills; hands-on experience with PrimeTime and hierarchical physical-design flows.
- End-to-end top-level digital integration and flat APR expertise using Innovus or ICC2.
- Fluent in Tcl and one of Python/Perl; working proficiency with agentic AI for engineering, including AI assistants, MCP-based tool integration, and workflow automation.
Nice to have
- Master’s degree or Ph.D. in Computer Engineering or Electrical Engineering.
- Multi-partition SoC or memory integration experience, clock planning, memory or mixed-signal design, DFT familiarity, EDA-vendor AI tools, or methodology/CAD contributions.
Pay
$145,000.00 - $246,000.00 a year (USD, base salary)
Tools
PrimeTime, Cadence Innovus, Synopsys ICC2, Design Compiler, Genus, Calibre, Tcl, Python
AI focus
Use and extend Micron’s internal AI toolkit for engineering work; apply AI-powered assistants, MCP-based tool integration, and workflow automation. Familiarity with EDA-vendor AI tools is preferred.
Model-written summary · the original posting is authoritative