Micron
Staff SoC DFT Engineer, HBM
$146K–$247K
Folsom, CA +1 · Staff · Full-time · Posted Oct 30, 2026
- Location
- Folsom, CA
Richardson, TX - Experience
- Seven or more years of relevant experience in SoC design, DFT, or implementation for complex digital ASICs or SoCs.
- Education
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
About the job
Owns DFT architecture, implementation, and signoff for HBM SoC base-die designs, enabling manufacturability, testability, and silicon bring-up.
What you'll do
- Define, implement, and integrate SoC-level scan, MBIST/LBIST, boundary scan (JTAG), and test access architectures.
- Drive DFT signoff, including checks, ATPG readiness, coverage closure, and collaboration on physical design closure.
- Partner with design, verification, product engineering, test, manufacturing, and CAD teams on debug, bring-up, and DFT flow improvements.
What they ask for
- Hands-on SoC DFT architecture and implementation experience, including scan insertion, MBIST/LBIST concepts, boundary scan (JTAG), and ATPG.
- Experience across full RTL-to-GDS SoC flows and collaboration with synthesis, STA, and physical design teams.
- Proficiency with industry-standard DFT and implementation EDA tools from Siemens, Synopsys, and/or Cadence.
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
Nice to have
- Experience with large SoCs integrating multiple IP blocks and subsystems; strong RTL debugging and analysis skills.
- Python, Tcl, or Perl scripting; familiarity with DRAM, HBM, and related JEDEC specifications.
Pay
$146,000.00 - $247,000.00 USD a year (base salary)
Tools
MBIST, LBIST, JTAG, ATPG, RTL, Siemens, Synopsys, Cadence
Model-written summary · the original posting is authoritative