Microsoft
Design Verification Engineer
$102K–$219K
Raleigh, NC +1 · On-site · Full-time · Posted Oct 12, 2026
- Location
- Raleigh, NC
Austin, TX - Experience
- Required: 1+ year with a master's degree, or 2+ years with a bachelor's degree, or equivalent experience. Preferred alternatives include 3+ years of related technical engineering experience, bachelor's or master's plus 3+ years of technical engineering or internship experience, or a doctorate.
- Education
- Master's or bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field; or equivalent experience.
About the job
Verifies complex silicon IP and designs through pre-silicon testing, coverage closure, debugging, and collaboration across hardware teams.
What you'll do
- Plan and execute verification using constrained-random environments, tests, or formal methods; identify scenarios and functional coverage.
- Analyze failures, close coverage gaps, and collaborate with design and cross-functional teams to deliver functionally correct products.
- Support chip bring-up with test firmware and improve validation methods and tools.
What they ask for
- Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year of technical engineering experience; OR bachelor's degree in one of those fields and 2+ years of technical engineering experience; OR equivalent experience.
- Meet Microsoft, customer, and/or government security screening requirements, including the Microsoft Cloud Background Check.
- Provide citizenship or qualifying residency/protected-status documentation for export-control eligibility assessment.
Nice to have
- Experience with full-cycle pre-silicon verification of IPs, subsystems, or SoCs, and creating/debugging IP/SoC-level tests.
- Knowledge of verification methods, chip or computer architecture, scripting, formal verification, Assembly, startup code, linker scripts, or Makefiles.
Pay
USD $102,100 - $202,200 per year (base salary); USD $133,800 - $219,200 per year (base salary)
Tools
SystemVerilog, UVM, SVA, C/C++, Python, Ruby, Perl, Makefiles
Model-written summary · the original posting is authoritative