Logic Design Engineer

What you'll do

• Develop and integrate RTL for SoC clock-controller functional blocks; perform timing closure, lint, CDC, synthesis, and low-power checks.
• Work with verification, physical design, design-for-test, and other teams; write basic tests, debug features, and automate tasks with scripting.
• Use AI to improve process and development efficiency, and deliver high-quality functional blocks on schedule.

What they ask for

• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year(s) technical engineering experience; OR bachelor's degree in one of these fields or a related field and 2+ years technical engineering experience; OR equivalent experience.
• Ability to meet Microsoft, customer, and/or government security screening requirements, including the Microsoft Cloud Background Check.
• Provide proof of citizenship, U.S. permanent residency, or other protected status for export-control eligibility assessment.

Nice to have

• Minimum 2+ years of logic design experience; knowledge of logic design flow, RTL, synthesis, timing constraints, timing closure, and low-power analysis.
• Verilog/System Verilog proficiency; clock-controller IP experience; familiarity with ARM protocols, Formal Equivalence Verification, or Power Analysis.

Pay

USD $102,100 - $202,200 per year (base salary); USD $133,800 - $219,200 per year (base salary)

Tools

RTL, CDC, Synthesis, Low Power Intent, UPF, Verilog/System Verilog, VCLP, Verilog simulators

AI focus

Use AI to gain efficiency within process and development.