Microsoft
Principal Silicon Architect
$143K–$304K
Mountain View, CA +4 · On-site · Principal · Full-time · Posted Oct 28, 2026
- Location
- Mountain View, CA
Redmond, WA
Austin, TX
Hillsboro, OR
Raleigh, NC - Experience
- 3+ years with a doctorate, 6+ years with a master's degree, or 8+ years with a bachelor's degree; equivalent experience accepted. Preferred: 10+ years of architecture and design experience in large-scale SoC.
- Education
- Doctorate, master's, or bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field; or equivalent experience.
About the job
Leads architecture and development of NoC, memory, and interconnect subsystems for high-performance AI and compute SoCs, from early specifications through validation and bring-up.
What you'll do
- Define SoC address maps, memory hierarchies, connectivity, and scalable data-movement architectures.
- Evaluate third-party IP, silicon technologies, and vendor solutions; guide performance modeling and design tradeoffs.
- Coordinate with cross-functional teams and guide implementation, verification, validation, and post-silicon performance characterization.
What they ask for
- Doctorate in a related field and 3+ years of technical engineering experience, or master's degree and 6+ years, or bachelor's degree and 8+ years, or equivalent experience.
- Meet Microsoft, customer, and/or government security screening requirements, including the Microsoft Cloud Background Check.
- Provide citizenship or eligible residency/protected-status documentation for export-control eligibility assessment.
Nice to have
- 10+ years of architecture and design experience in large-scale SoC.
- Experience with SoC architecture, interconnect and memory hierarchy, cache coherency, data-center SoCs, or related silicon features.
Pay
USD $142,800 - $274,800 per year (base salary); USD $188,000 - $304,200 per year (base salary)
Tools
ASIC, SoC, Network-on-Chip (NoC), IP, caches, cache coherency, die-to-die interconnect, RAS
AI focus
Architects NoC, memory, and interconnect subsystems for high-performance AI and compute SoCs.
Model-written summary · the original posting is authoritative