Microsoft
Principal Silicon Design Verification Engineer
$143K–$304K
Santa Clara, CA +6 · On-site · Principal · Full-time · Posted Oct 20, 2026
- Location
- Santa Clara, CA
Mountain View, CA
Hillsboro, OR
Austin, TX
Boise, ID
San Diego, CA
Redmond, WA - Experience
- 3+ years with a doctorate, 6+ years with a master's degree, or 8+ years with a bachelor's degree; equivalent experience is also accepted.
- Education
- Doctorate, master's, or bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field; or equivalent experience.
About the job
Validates PCIe IP at block, cluster, or full-chip level, develops test plans and tests, and improves verification workflows.
What you'll do
- Develop test plans and unit tests for functional validation using UVM/C test benches and VIP.
- Create and manage regression suites, debug failures, and drive timely resolution.
- Improve validation efficiency through methodologies and tools.
What they ask for
- Doctorate in a related field plus 3+ years of technical engineering experience, or master's degree plus 6+ years, or bachelor's degree plus 8+ years, or equivalent experience.
- Meet Microsoft, customer, and/or government security screening requirements, including the Microsoft Cloud Background Check.
- Provide citizenship, U.S. residency, or other protected-status documentation to assess eligibility for access to export-controlled information.
Nice to have
- Experience with PCIe protocol verification, especially Gen6/Gen7, or related standards such as NVMe or RDMA.
- Experience with Cluster, SoC, or Fullchip verification; PCIe Transaction and Data Link Layer verification; or UVM testbench and regression work.
Pay
USD $142,800 - $274,800 per year (base salary); USD $188,000 - $304,200 per year (base salary)
Tools
PCIe, UVM/C, VIP, Verilog, System Verilog, NVMe, RDMA
Model-written summary · the original posting is authoritative